(View in PDF
The International Symposium on Asynchronous Circuits and
provides a high-quality forum for scientists and engineers to
their latest research findings. Authors are invited to
papers on all aspects of asynchronous design. Topics of
include, but are not limited to:
Mixed synchronous/asynchronous architectures,
interfaces, and circuits
High-speed/low-power asynchronous logic, memories,
High-level design and synthesis of self-timed
Physical design of unclocked logic and pipelines
Formal methods for correctness and performance
analysis of asynchronous designs
Test, reliability, security, and radiation tolerance
CAD for asynchronous design and validation
Asynchronous System-on-Chip (SoC), System-in-Package
(SiP), and Network-on-Chip (NoC)
Novel asynchronous architectures
Asynchrony and latency tolerance in system-level
Papers should be submitted via the conference web site.
should not exceed ten pages in IEEE double-column format.
exceed the length limit may not be reviewed. Papers will
by the program committee and reviews will be based on scientific
innovation, relevance, and presentation. New idea papers
encouraged, and the program committee recognizes that such
contain less evaluation than papers in established areas.
papers will be published in an IEEE proceedings and distributed
For submission information, visit the
Paper Submission page.
|Sep 25, 2006
|Oct 2, 2006 (firm)
|Notification of acceptance:
|Nov 20, 2006
2007, 5pm EST ("drop dead" deadline)
Jan 1, 2007 is a hard deadline for submitting the final
IEEEXplore-compliant camera-ready version of your paper,
as well as the copyright form. No extensions will
be granted. You are advised, however, to submit
several days earlier, as any font/formatting problems
discovered can take time to resolve.
Paper submission is now closed. Reviewer website can be
All deadlines are 11:59pm Pacific Time [GMT-7]
|Abstract of up to 150 words,
10 pages or fewer including figures,
single-spaced, 10pt or larger font size,
IEEE double-column conference format.