Demo Session

ASYNC 2007, 13th IEEE International Symposium on Asynchronous Circuits and Systems

March 12-14, 2007, University of California at Berkeley, USA
Bechtel Engineering Center - Sibley Auditorium & Garbarini Lounge

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The Call for Demonstration is now extended to 16th February

About the Industrial and Demo Session

There will be a technical demonstration session on the afternoon of the first day of the conference. This session provides focused opportunity for our industrial partners to demonstrate advances in technology and marketing, and to mingle and interact directly with the students and faculty. The session is also open to students and faculty to demonstrate their interesting new technology.

During this session, it will be possible for industry and students to present running circuit demonstrations or CAD tools. Posters or even small booths for our industrials partners are welcome in order to present the company and demonstrations. Lastly, in order to introduce the various industrial and research groups who will participate in this event, we will have a short presentation with the list of demos and a quick introduction of each of them.

Please fill out the Call for Demonstration form and submit it via e-mail by clicking on the "Submit by Email" button on the form. We request that you submit your request by January 26 (Extended to Feb 16th) so that we can advertise and organize this session.

Scheduled demonstrations on Monday March 12, 2007

The Async'07 conference attendees will participate to the following demonstrations during the conference demo session which is scheduled on Monday March 12th, at 04:45 PM :

Demonstrator Demo Name Description
Silistix: CHAINworks tool chain Silistix will present CHAINworks™, a suite of software tools for the design and synthesis of customized on-chip interconnect using self-timed (clock-less) circuits. On-chip interconnects developed with their technology eliminate many of the biggest design problems you face every day; timing closure, power consumption, and overall design complexity.
Handshake Solutions Handshake Solutions tools and circuits Handshake Solutions is going to present the TiDE (Timeless Design Environment) tool set for designing asynchronous circuits starting from Haste. In addition some demo boards may be shown with FPGA implementations of some asynchronous IP blocks. The latter is subject to availability on this day.
Fulcrum Microsystems FocalPoint Evaluation Platform Fulcrum will demonstrate a 24 port 10Gb Ethernet switch. The system uses Fulcrum FocalPoint FM2224 chip, which was designed using a majority of asynchronous circuitry.
Codetronix Mobius Rapid Development Tools Codetronix will demonstrate high-level simulation and compilation of algorithms into correct-by-construction asynchronous NCL or synchronous FPGA circuits. Mobius simultaneously provides high-productivity with high Quality of Results compared to hand-crafted circuits.
Tima Secure crypto-processors against power and fault attacks We want to point out how QDI logic can be efficiently used to improve circuits' resistance against power attacks and fault injections. The demonstrated circuit implements a Clock-Less AES crypto-processor architecture, compliant with the NIST standard: 128 bit data blocks and 128, 192 or 256 bit keys. The circuit implements a standard bus interface enabling an easy connection to any synchronous microprocessors or ASICs. The circuit, powered at 1.2 volt, ciphers a 128 bit date using a 128 bit key in less than 1 µs which corresponds to a ciphering rate of about 140 Mbits per second. Due to the robustness of the clock-less Quasi Delay Insensitive logic used to design the chip, the circuit is functional within a wide voltage range, from 1.2 Volt down to 0.4 Volt. This feature is particularly interesting in secure and low-power applications. Power and fault attacks resistance will be discussed by the demo's presenter.
University of North Carolina at Chapel Hill

Gennette Gill

High-Speed Fully-Pipelined GCD Chip We will demonstrate the operation of a high-speed asynchronous greatest common divisor (GCD) chip. This chip is a case study with several objectives: (i) demonstration in silicon of the high-speed MOUSETRAP pipeline style ; (ii) evaluation of loop pipelining, a recent high-level synthesis and optimization approach for iterative algorithms ; and (iii) validation of a recent test approach for stuck-at faults and timing constraint violations in high-speed pipelines. The chip was fabricated in a 0.13µm CMOS process, using standard cells and with full testability support. The fabricated parts were found to be fully functional, with throughputs of up to 1.01 Giga operations/second at nominal operating conditions. A careful analysis, however, indicates that the chip's internal core datapath was actually capable of up to 2.07 Giga operations/second.
Sun Microsystems Laboratories

VLSI Research Group

Jo Ebergen


Proximity Communication


We present two posters explaining the principles of Proximity Communication, a demo of a running chip, and a few other Proximity Communication chips that people can hold and look at.
Intel Corporation

David Bormann

GALS Test Chip We demonstrate a Globally Asynchronous Locally Synchronous test chip fabricated on an Intel 130nm silicon process technology. The prototype contains a configurable GALS pipeline than can be tuned to emulate the operation of many different types of algorithms. The Asynchronous Wrapper approach successfully produced a fully functional design on first silicon.

Other demos from companies, academics and universities are still welcome. The call for demonstration has been extended to 16th February. Please fill out the Call for Demonstration PDF form above.


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