Program

ASYNC 2007, 13th IEEE International Symposium on Asynchronous Circuits and Systems

March 12-14, 2007, University of California at Berkeley, USA
Bechtel Engineering Center - Sibley Auditorium & Garbarini Lounge

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Preliminary Program

Sunday, March 11, 2007

07:00-10:00 PM Welcome Reception in Hearst Memorial Mining Building at UCB

(same location as lunch Monday and Wednesday)

Monday, March 12, 2007

08:00-08:30 AM Breakfast
08:30-09:00 AM Welcome Session:
  • ASYNC2007 chairs (slides)
  • EECS chair Prof. Edward Lee (slides)
09:00-10:00 AM Invited Speaker I

Signaling with Conserved Quantities: Two Realizations in CMOS and Superconducting Flux Quantum Logic  (slides)

James T. Kajiya, Microsoft Research

10:00-10:30 AM BREAK
10:30-12:00 PM Technical Session 1: High-speed Links/Signaling
  • High rate wave-pipelined asynchronous on-chip bit-serial data link. Rostislav (Reuven) Dobkin, Yevgeny Perelman, Tuvia Liran, Ran Ginosar and Avinoam Kolodny (Slides)
  • Notes On Pulse Signaling. Jo Ebergen, Steve Furber, Arash Saifhashemi, Naela Nissar and Alex Chow (Slides)
  • A Jitter Attenuating Timing. Chain Suwen Yang, Mark R. Greenstreet and Jihong Ren (Slides)
12:00-01:30 PM LUNCH
01:30-03:00 PM Technical Session 2: Asynchronous Applications
  • The Vortex: An Asynchronous Superscalar Processor. Andrew Lines (Slides)
  • Design of a High-Speed Asynchronous Turbo Decoder. Pankaj Golani, Georgios Dimou, Mallika Prakash and Peter Beerel (Slides)
  • Asynchronous on Chip Communication: Explorations on the Intel®PXA27x Processor Peripheral Bus. Andrew Scott, Mark Schuelein, Marly Roncken, Jin-Jer Hwan, John Bainbridge, John Mawer, David Jackson and Andrew Bardsley (Slides)
03:00-03:30 PM BREAK 
03:30-04:30 PM Technical Session 3: Verification
  • Formal Verification of CHP Specifications with CADP -- Illustration on an Asynchronous Network-on-Chip. Gwen Salaün, Wendelin Serwe, Yvain Thonnart and Pascal Vivet (Slides)
  • Gate-level modelling and verification of asynchronous circuits using CSP_M and FDR. Mark Josephs (Slides)
04:30-04:45 PM BREAK
04:45-06:00 PM Innovations and Demo Session
DINNER Not Provided

Handouts contain nearby restaurant selection ordered by price/food-type.

We will reserve a few via sign-up lists, and let students guide the groups to them

Tuesday, March 13, 2007

08:00-08:30 AM Breakfast
08:30-09:30 AM Invited Speaker II

Thinking Outside the Box in Geometry and Art (Slides)

Carlo H. Sequin, University of California, Berkeley

09:30-10:00 AM BREAK
10:00-11:00 AM Technical Session 4: Novel Circuits
  • The Design of a Genetic Muller C-Element. Nam-Phuong Nguyen, Hiroyuki Kuwahara, Chris Myers and James Keener (Slides)
  • Delay/Phase Regeneration Circuits. Crescenzo D'Alessandro, Andrey Mokhov, Alex Bystrov and Alex Yakovlev (Slides)
11:00-11:30 AM BREAK
11:30-12:30 PM Technical Session 5: Synthesis
  • Area Optimizations for Dual-Rail Circuits using Relative-Timing Analysis. Tiberiu Chelcea, Girish Venkataramani and Seth Goldstein (Slides)
  • A Cycle-Based Decomposition Method for Burst-Mode Asynchronous Controllers. Melinda Y. Agyekum and Steven M. Nowick (Slides)
12:30-02:00 PM LUNCH: Not Provided

As for dinner Monday, we'll pick a few lunch places with student guides to these. Please use this time to sync-up with your partner for the social afternoon event

02:00-10:00 PM Social event

BART/Cable-car Student-led trip to Cable Car Museum and Dinner

Invited Speaker III at dinner

Too Many Robots, Too Little Time

Steve Jacobsen, Sarcos, Inc.

Wednesday, March 14, 2007

08:30-09:00 AM Breakfast
09:00-10:00 AM Invited Speaker IV

Statistical Variations Are Inevitable – Can We Cope With Them?

Kevin Nowka, IBM Austin Research Laboratory

10:00-10:30 AM BREAK
10:30-12:00 PM Technical Session 6: Test and Measurement
  • A Configurable Asynchronous Pseudorandom Bit Sequence Generator. Alex Chow, William Coates and David Hopkins (Slides)
  • On-chip samplers for test and debug of asynchronous circuits. Frankie Liu, Ron Ho and Robert Drost (Slides)
  • A High Resolution Flash Time-to-Digital Converter Utilizing Process Variability. Nikolaos Minas, David Kinniment, Keith Heron and Gordon Russell (Slides)
12:00-01:30 PM LUNCH
01:30-03:00 PM Technical Session 7: Interfaces
  • Demystifying Data-Driven and Pausible Clocking Schemes. Robert Mullins and Simon Moore (Slides)
  • Efficient Asynchronous Protocol Converters for Two-Phase Delay-Insensitive Global Communication. Amitava Mitra, William F. McLaughlin and Steven M. Nowick (Slides)
  • Low Latency Clock Domain Transfer for Simultaneously Mesochronous, Plesiochronous and Heterochronous Interfaces. Wade Williams and Philip Madrid (Slides)
03:00-03:30 PM BREAK
03:30-04:00 PM Best Paper Award and Closing Session

 


Invited Talks

Invited Talk 1

Signaling with Conserved Quantities: Two Realizations in CMOS and Superconducting Flux Quantum Logic

James T. Kajiya, Microsoft Research

A simple scheme for single rail asynchronous data transmission and signaling relying on the management and transfer of conserved quantities is presented. The conserved quantity is dependent on the kind of logic family used: mass for fluidic logic, charge for CMOS logic, and flux for superconducting flux quantum logic.

Although superconducting flux quantum logic has appeared in these proceedings before, we point out that a range of alternative circuit technologies exist that present a tantalizing opportunity for the ASYNC community. These logic technologies have an exceptional combination of low power (10^-18 J/pulse) with high speed (50-500GHz), and are fundamentally based on asynchronous signaling, not levels.

 

Invited Talk 2

Thinking Outside the Box in Geometry and Art

Carlo H. Sequin, University of California, Berkeley

Dr. Sequin has been a CAD tool builder for the last 30 years. He has participated in the design of solid-state filters and image sensors, institutional research buildings, mechanical toys, and, more recently, abstract geometrical sculptures.

Geometric shapes have fascinated people for thousands of years. With the development of coding theories involving more than three dimensions, and String Theory postulating a universe of ten or more dimensions, geometry now extends to realms that are sometimes hard to visualize.

This talk will express the wonder and beauty that Prof Sequin finds in his "Artistic Geometry" and the way he uses the computer in interactive ways as an amplifier of his creativity to reach beyond an initial design concept. He will illustrate his remarks with many pictures and maquettes.

 

Invited Talk 3

Too Many Robots, Too Little Time

Steve Jacobsen, Sarcos, Inc.

Robots not only can be useful, but also can entertain. From the robot fountains at Bellagio to humanoid figures and Jurassic park dinosaurs, Sarcos has applied new technology to make things move in complex and entertaining ways. Major improvements in the cost and reliability of sensors and actuators have made these projects possible; improvements that also apply to more practical work in robots for demanding and dangerous tasks. Along the way we've learned much about the behavior of people interacting with robots - our engineers, our artists, our clients and their audiences.

Dr Jacobsen will illustrate the talk with moving images of a variety of his robots in action.

 

Invited Talk 4

Statistical Variations Are Inevitable – Can We Cope With Them?

Kevin Nowka, IBM Austin Research Laboratory

The ever-decreasing size of wires and transistors on VLSI chips has driven the revolution in electronics over the past several decades. The features in advanced chips are now so small that variations in numbers of photons and numbers of atoms matter. Lithography of subwavelength device dimensions and statistical variations in the numbers of dopant atoms that elicit transistor behavior result in significant variation in the electrical properties of tiny transistors. Such variations are an inevitable consequence of miniaturization revealing the quantized nature of light and matter.

CMOS technology process improvements cannot be expected to reduce such statistical variations in tiny artifacts. Instead, we must design systems that work in spite of such variations. We must develop characterization structures and models to understand the resultant device behavior, extend current test methods to detect statistical outliers and introduce increasing amounts of redundancy to allow identification and replacement of parts with excessive variation. Most important of all, we must develop and employ design processes and design tools to produce variation resilient designs. The circuits and tools developed to build asynchronous systems may help.

This talk will focus on the three sources of variation in CMOS circuits: process, environment, and design-introduced variability. This talk will explore the extent to which these sources of variability affect the underpinnings of current design tools and practices such as cell-based composability, static timing, and sorting based on proxy circuits. Characterizing, modeling, and compensating for systematic and random variation will become a central feature of future systems designs.

 

 

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